50+ TOP VHDL PROJECT

* List of Top VHDL Project for ECE Students *

Modulator for digital terrestrial television according to the DTMB standard CAN Controller Design Router Architecture for Junction Based Source Routing Design Space Exploration Of Field Programmable Counter Mobile Broadband Receiver OBJECT TRACKING ALGORITHM Hardware/Software Runtime Environment for Reconfigurable Computers Face Detection System Using Haar Classifiers Fast Hardware Design Space Exploration Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits HIGH SPEED 4 BIT SFQ MULTIPLIER Universal Cryptography Processor for Smart Cards HIGH SPEED MULTIPLIER USING SPURIOUS POWER SUPPRESSION LOSSLESS DATA COMPRESSION HARDWARE ARCHITECTURE VLSI Architecture For Removal Of Impulse Noise In Image PROCESSOR ARCHITECTURES FOR MULTIMEDIA High Speed Multiplier – Accumulator Using SPST Power Efficient Logic Circuit Design Data Transfer for AMBA Bus ATM Knockout Switch Concentrator Synthesis of Asynchronous Circuits AMBA AHB compliant Memory Controller Ripple Carry and Carry Skip Adders 32bit Floating Point Arithmetic Unit CRC Circuit Architecture ON-CHIP PERMUTATION NETWORK FOR MULTIPROCESSOR VLSI Systolic Array Multiplier for signal processing Applications Floating point Arithmetic Logic Unit DDR SDRAM CONTROLLER FFT Processor Using Radix-4 Algorithm 32 bit RISC Processor SMART SENSOR Fuzzy based PID Controller Stepper Motor Controller I2C Bus Controller Solar Power Saving System for Street Lights and Automatic Traffic Controller Fuzzy Based Mobile Robot Controller Real time Traffic Light Control System Digital Space Vector PWM Three Phase Voltage Source Inverter Complex Multiplier Using Advance Algorithm Discrete Wavelet Transform (DWT) for Image Compression Gabor Filter for Fingerprint Recognition Floating Point Fused Add-Subtract and multiplier Units ORTHOGONAL CODE CONVOLUTION CAPABILITIES Flip -Flops for High Performance VLSI Applications Low Power Video Compression Achitecture Power Gating Implementation with Body-Tied Triple-Well Structure UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER LOW POWER MULTIPLIER USING COMPOUND CONSTANT DELAY LOGIC JPEG IMAGE COMPRESSION TECHNIQUE IMPLEMENTATION ON FPGA EFFICIENT FFT/IFFT IMPLEMENTATION TECHNIQUE FOR OFDM ON FPGA    A NEW VLSI ARCHITECTURE OF PARALLEL MULTIPLIER–ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM  IMPROVEMENT OF THE ORTHOGONAL CODE CONVOLUTION CAPABILITIES USING FPGA IMPLEMENTATION OPTIMIZED SOFTWARE IMPLEMENTATION OF A FULL-RATE IEEE 802.11A COMPLIANT DIGITAL BASEBAND TRANSMITTER ON A DIGITAL SIGNAL PROCESSOR IMPLEMENTATION OF IEEE 802.11A WLAN BASEBAND PROCESSOR  FPGA IMPLEMENTATIONS OF THE HUMMINGBIRD CRYPTOGRAPHIC ALGORITHM  DESIGN OF LOW POWER AND HIGH SPEED CONFIGURABLE BOOTH MULTIPLIER   VLSI IMPLEMENTATION OF HIGH SPEED AND HIGH RESOLUTION FFT ALGORITHM BASED ON RADIX 2 FOR DSP APPLICATION.  FPGA IMPLEMENTATION(S) OF A SCALABLE ENCRYPTION ALGORITHM  IMPLEMENTATION OF OFDM ON FPGA.